VS1033 Datasheet, PDF (22/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
7. SPI BUSES
7.7 SPI Examples with SM SDINEW and SM SDISHARED set
7.7.1 Two SCI Writes
SCI Write 1
SCI Write 2
XCS
0
1
2
3
SCK
SI
0
0
0
0
DREQ
30 31
10
X
32 33
61 62 63
0
0
2
1
0
X
DREQ up before finishing next SCI write
Figure 9: Two SCI Operations.
Figure 9 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between
the writes. Also DREQ must be respected as shown in the figure.
7.7.2 Two SDI Bytes
SDI Byte 1
XCS
0
1
2
3
SCK
7
6
5
4
3
SI
67
10
SDI Byte 2
8
9
13 14 15
7
6
5
2
1
0
X
DREQ
Figure 10: Two SDI Bytes.
SDI data is synchronized with a raising edge of xCS as shown in Figure 10. However, every byte doesn’t
need separate synchronization.
Version 0.6, 2005-01-05
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