VS1033 Datasheet, PDF (31/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
8. FUNCTIONAL DESCRIPTION
8.5 Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are always 16
bits. VS1033 is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
• control of the operation mode, clock, and builtin effects
• access to status information and header data
• access to encoded digital data
• uploading user programs
8.6 SCI Registers
VS1033 sets DREQ low when it detects an SCI operation and restores it when it has processed the
operation. The duration depends on the operation. Do not start a new SCI/SDI operation before DREQ
is high again. If DREQ is low when an SCI operation is performed, it also stays low after SCI operation
processing.
Reg Type Reset
SCI registers, prefix SCI
Time¹ Abbrev[bits]
Description
0x0 rw 0x800
0x1 rw 0x0C³
70 CLKI⁴ MODE
40 CLKI STATUS
Mode control
Status of VS1033
0x2 rw 0
0x3 rw 0
2100 CLKI BASS
11000 XTALI⁵ CLOCKF
Built-in bass/treble enhancer
Clock freq + multiplier
0x4 rw 0
40 CLKI DECODE TIME Decode time in seconds
0x5 rw 0
3200 CLKI AUDATA
Misc. audio data
0x6 rw 0
80 CLKI WRAM
RAM write/read
0x7 rw 0
80 CLKI WRAMADDR Base address for RAM write/read
0x8 r 0
- HDAT0
Stream header data 0
0x9 r 0
0xA rw 0
- HDAT1
3200 CLKI² AIADDR
Stream header data 1
Start address of application
0xB rw 0
0xC rw 0
0xD rw 0
0xE rw 0
0xF rw 0
2100 CLKI
50 CLKI²
50 CLKI²
50 CLKI²
50 CLKI²
VOL
AICTRL0
AICTRL1
AICTRL2
AICTRL3
Volume control
Application control register 0
Application control register 1
Application control register 2
Application control register 3
1 _{This is the worst-case time that DREQ stays low after writing to this register. The user may choose to}
skip the DREQ check for those register writes that take less than 100 clock cycles to execute.
2 _{In addition, the cycles spent in the user application routine must be counted.}
3 _{Firmware changes the value of this register immediately to 0x48, and in less than 100 ms to 0x40.}
4 _{When mode register write specifies a software reset the worst-case time is 16600 XTALI cycles.}
5 _{Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not a}
good idea to send SCI or SDI bits while this register update is in progress.
Version 0.6, 2005-01-05
31