VS1033 Datasheet, PDF (56/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
10. VS1033 REGISTERS
10.8 Interrupt Registers
Reg
0xC01A
0xC01B
0xC01C
0xC01D
Type
rw
w
w
rw
Reset
0
0
0
0
Interrupt registers, prefix INT
Abbrev[bits]
Description
ENABLE[7:0]
GLOB DIS[-]
Interrupt enable
Write to add to interrupt counter
GLOB ENA[-]
Write to subtract from interrupt counter
COUNTER[4:0] Interrupt counter
INT ENABLE controls the interrupts. The control bits are as follows:
Name
INT EN TIM1
INT EN TIM0
INT EN RX
INT EN TX
INT EN MODU
INT EN SDI
INT EN SCI
INT EN DAC
INT ENABLE bits
Bits Description
7 Enable Timer 1 interrupt
6 Enable Timer 0 interrupt
5 Enable UART RX interrupt
4 Enable UART TX interrupt
3 Enable AD modulator interrupt
2 Enable Data interrupt
1 Enable SCI interrupt
0 Enable DAC interrupt
Note: It may take upto 6 clock cycles before changing INT ENABLE has any effect.
Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectively
disables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect.
Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTER
already was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are re-
stored. An interrupt routine should always write to this register as the last thing it does, because in-
terrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the
responsibility of the user. It may take upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the register
is not 0, interrupts are disabled.
Version 0.6, 2005-01-05
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