NT256D64SH8B0GM Datasheet, PDF (5/15 Pages) List of Unclassifed Manufacturers – 200pin Unbuffered DDR SO-DIMM

NT256D64SH8B0GM
256MB : 32M x 64
PC2100 Unbuffered DDR SO-DIMM
Serial Presence Detect -- Part 1 of 2
32Mx64 SDRAM DIMM based on 16Mx16, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
Byte
Description
SPD Entry Value
DDR266B
Serial PD Data Entry
(Hexadecimal)
DDR266B
-75B
-75B
0 Number of Serial PD Bytes Written during Production
128
80
1 Total Number of Bytes in Serial PD device
256
08
2 Fundamental Memory Type
SDRAM DDR
07
3 Number of Row Addresses on Assembly
13
0D
4 Number of Column Addresses on Assembly
9
09
5 Number of DIMM Bank
2
02
6 Data Width of Assembly
X64
40
7 Data Width of Assembly (cont’)
X64
00
8 Voltage Interface Level of this Assembly
SSTL 2.5V
04
9 DDR SDRAM Device Cycle Time at CL=2.5
7.5ns
75
10 DDR SDRAM Device Access Time from Clock at CL=2.5
0.75ns
75
11 DIMM Configuration Type
Non-Parity
00
12 Refresh Rate/Type
SR/1x(7.8us)
82
13 Primary DDR SDRAM Width
X16
10
14 Error Checking DDR SDRAM Device Width
N/A
00
DDR SDRAM Device Attr: Min CLK Delay, Random Col
15
1 Clock
01
Access
16 DDR SDRAM Device Attributes: Burst Length Supported
2,4,8
0E
17 DDR SDRAM Device Attributes: Number of Device Banks
4
04
18 DDR SDRAM Device Attributes: CAS Latencies Supported
2/2.5
0C
19 DDR SDRAM Device Attributes: CS Latency
0
01
20 DDR SDRAM Device Attributes: WE Latency
1
02
21 DDR SDRAM Device Attributes:
Differential Clock
20
22 DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23 Minimum Clock Cycle at CL=2
10ns
A0
24 Maximum Data Access Time from Clock at CL=2
0.75ns
75
25 Minimum Clock Cycle Time at CL=1
N/A
00
26 Maximum Data Access Time from Clock at CL=1
N/A
00
27 Minimum Row Precharge Time (tRP)
20ns
50
28 Minimum Row Active to Row Active delay (tRRD)
15ns
3C
29 Minimum RAS to CAS delay (tRCD)
20ns
50
30 Minimum RAS Pulse Width (tRAS)
45ns
2D
31 Module Bank Density
128MB
20
32 Address and Command Setup Time Before Clock
0.9ns
90
33 Address and Command Hold Time After Clock
0.9ns
90
34 Data Input Setup Time Before Clock
0.5ns
50
35 Data Input Hold Time After Clock
0.5ns
50
36-61 Reserved
Undefined
00
62 SPD Revision
Initial
00
63 Checksum Data
A7
Note
REV 1.3
01/2003
5
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