NT256D64SH8B0GM Datasheet, PDF (11/15 Pages) List of Unclassifed Manufacturers – 200pin Unbuffered DDR SO-DIMM

NT256D64SH8B0GM
256MB : 32M x 64
PC2100 Unbuffered DDR SO-DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 °C ~ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
tAC
tDQSCK
tCH
tCL
tCK
tCK
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock cycle time
CL=2.5
CL=2
-75B
Min.
Max.
-0.75
+0.75
-0.75
+0.75
0.45
0.55
0.45
0.55
7.5
12
10
12
Unit Notes
ns
1-4
ns
1-4
tCK
1-4
tCK
1-4
ns
1-4
ns
1-4
tDH
DQ and DM input hold time
1-4,
0.5
ns
15, 16
tDS
DQ and DM input setup time
0.5
tDIPW DQ and DM input pulse width (each input)
1.75
1-4,
ns
15, 16
ns
1-4
tHZ
Data-out high-impedance time from CK/CK
-0.75
+0.75
ns 1-4, 5
tLZ
tDQSQ
tHP
Data-out low-impedance time from CK/CK
DQS-DQ skew (DQS & associated DQ signals)
Minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
tQH
tQHS
tDQSS
tDQSL,H
tDSS
tDSH
tMRD
Data output hold time from DQS
Data hold Skew Factor
Write command to 1st DQS latching transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
Mode register set command cycle time
tWPRES Write preamble setup time
tWPST
tWPRE
tIH
tIS
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
Address and control input setup time
(fast slew rate)
Address and control input hold time
tIH
(slow slew rate)
-0.75
tCH
or
tCL
tHP -
tQHS
0.75
0.35
0.2
0.2
2
0
0.40
0.25
0.9
0.9
1.0
+0.75
0.5
ns 1-4, 5
ns
1-4
tCK
1-4
0.75ns
1.25
0.60
tCK
1-4
tCK
1-4
tCK
1-4
tCK
1-4
tCK
1-4
tCK
1-4
tCK
1-4
ns 1-4, 7
tCK 1-4, 6
tCK
1-4
2-4, 9,
ns
11, 12
2-4, 9,
ns
11, 12
2-4,
ns 10, 11,
12, 14
REV 1.3
01/2003
11
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