NT256D64SH8B0GM Datasheet, PDF (10/15 Pages) List of Unclassifed Manufacturers – 200pin Unbuffered DDR SO-DIMM

NT256D64SH8B0GM
256MB : 32M x 64
PC2100 Unbuffered DDR SO-DIMM
Operating, Standby, and Refresh Currents
(TA = 0 °C ~ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
I DD0
Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC
(MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs
changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
I DD2P _{mode; CKE ≤ VIL (MAX); tCK = tCK (MIN)}
Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK =
I DD2N _{tCK (MIN); address and control inputs changing once per clock cycle}
Active Power-Down Standby Current: one bank active; power-down mode;
I DD3P _{CKE ≤ VIL (MAX); tCK = tCK (MIN)}
I DD3N
Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥
VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; address and control inputs changing once
per clock cycle
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL=2.5; tCK = tCK (MIN)
I DD5 Auto-Refresh Current: tRC = tRFC (MIN)
I DD6 Self-Refresh Current: CKE ≤ 0.2V
I DD7
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; tRC = tRC (min); IOUT = 0mA.
1. I DD specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ ns.
3. Enables on-chip refresh and address counters.
4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.
PC2100
(-75B)
500
620
80
200
160
400
1100
800
1200
24
1500
Unit Notes
mA
1, 2
mA
1, 2
mA
1, 2
mA
1, 2
mA
1, 2
mA
1, 2
mA
1, 2
mA
1, 2
mA 1, 2, 4
mA
1, 2
mA
1, 2
REV 1.3
01/2003
10
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.