NT256D64SH8B0GM Datasheet, PDF (1/15 Pages) List of Unclassifed Manufacturers – 200pin Unbuffered DDR SO-DIMM

NT256D64SH8B0GM
256MB : 32M x 64
PC2100 Unbuffered DDR SO-DIMM
200pin Unbuffered DDR SO-DIMM Based on DDR266 16Mx16 SDRAM
Features
• JEDEC Standard 200-Pin Small Outline Dual In-Line Memory
Module (SO-DIMM)
• 32Mx64 Double Unbuffered DDR SO-DIMM based on 16Mx16
DDR SDRAM.
• Performance:
PC2100
Speed Sort
DIMM CAS Latency
-75B Unit
2.5
f CK Clock Frequency
133 MHz
t CK Clock Cycle
7.5 ns
f DQ DQ Burst Frequency 266 MHz
• Intended for 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
• SDRAMs have 4 internal banks for concurrent operation
• Module has two physical banks
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock
transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/9/2 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
Description
NT256D64SH8B0GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory
Module (SO-DIMM), organized as a two-bank 32Mx64 high-speed memory array. The module uses eight 16Mx16 DDR SDRAMs in 400
mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The
use of these common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a
high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.
The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to
266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
NT256D64SH8B0GM-75B
Speed
133MHz (7.5ns @ CL = 2.5)
100MHz (10ns @ CL = 2)
DDR266B
PC2100
Organization
32Mx64
Leads
Gold
Power
2.5V
REV 1.3
01/2003
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.