ICM200E Datasheet, PDF (29/32 Pages) List of Unclassifed Manufacturers – Megapixel (UXGA) Digital Color CMOS Image Sensor

ICM200E
2 Megapixel (UXGA) Digital Color CMOS Image Sensor
Preliminary Data Sheet V1.1
QSVGA Subsampling Mode Timing
For the default QSVGA line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC
signal will be low for 16 PCLK clock cycles. After 25 PCLK clock cycles, DOUT [9:0] will output 4 cycles
of dummy pixel data followed by 400 cycles of image data, and followed by another 2 cycles of dummy
pixel data. Another 19 cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure 13.
Figure 13. Default QSVGA Line Timing for 450 PCLKs
QSVGA Subsampling Mode Frame Timing
For the default QSVGA frame timing, the timing unit for the frame is derived from one line-time unit,
which is 450 PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal
will be low for 3 line-time units. Four line-time units from the start of the frame, DOUT [9:0] will output 3
lines of dummy pixel data followed by 300 lines of image data, and followed by another 2 lines of dummy
pixel data. The VSYNC signal will be de-asserted again to start a new frame after another 15 line-time
units. See Figure 14.
Figure 14. Default QSVGA Frame Timing - Set Registers 0x14/0x15 to 0x0010 (H)
Copyright 2004, IC Media Corporation
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Page 29
9/22/2004