ICM200E Datasheet, PDF (28/32 Pages) List of Unclassifed Manufacturers – Megapixel (UXGA) Digital Color CMOS Image Sensor

ICM200E
2 Megapixel (UXGA) Digital Color CMOS Image Sensor
Preliminary Data Sheet V1.1
SVGA Subsampling Mode Timing
For the default SVGA line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC signal
will be low for 32 PCLK clock cycles. After 50 PCLK clock cycles, DOUT [9:0] will output six cycles of
dummy pixel data followed by 800 cycles of image data, and followed by another 4 cycles of dummy pixel
data. Another 40 cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure 11.
Figure 11. Default SVGA Line Timing for 900 PCLKs
SVGA Subsampling Mode Frame Timing
For the default SVGA frame timing, the timing unit for the frame is derived from one line-time unit, which
are 900 PCLKs. Frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal will be
low for 3 line-time units. Eight line-time units from the start of the frame, DOUT [9:0] will output 6 lines
of dummy pixel data, followed by 600 lines of image data, and followed by another 4 lines of dummy pixel
data. The VSYNC signal will be de-asserted again to start a new frame after another 32 line-time units. See
Figure 12.
Figure 12. Default SVGA Frame Timing – Set Registers 0x14/0x15 to 0x0010 (H)
Copyright 2004, IC Media Corporation
http://www.ic-media.com/
Page 28
9/22/2004