ICM200E Datasheet, PDF (27/32 Pages) List of Unclassifed Manufacturers – Megapixel (UXGA) Digital Color CMOS Image Sensor

ICM200E
2 Megapixel (UXGA) Digital Color CMOS Image Sensor
Preliminary Data Sheet V1.1
UXGA Mode Line Timing
For the default UXGA line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC signal
will be low for 64 PCLK clock cycles. At 100 PCLK clock cycles, DOUT [9:0] will output 10 cycles of
dummy pixel data, followed by 1600 cycles of image data, and followed by another 10 dummy pixel data.
Another 80 cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure 9.
Figure 9. Default UXGA Line Timing for 1800 PCLKs
UXGA Mode Frame Timing
For the default UXGA frame timing, frame timing is derived from one line-time unit, which is 1800
PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal will be low for
3 line-time units. Sixteen line-time units from the start of the frame, DOUT [9:0] will output 10 lines of
dummy pixel data, followed by 1200 lines of image data, and followed by another 10 lines of dummy pixel
data. The VSYNC signal will be de-asserted again to start a new frame after another 64 line-time units. See
Figure 10.
Figure 10. Default UXGA Frame Timing - Set Registers 0x4/0x15 to 0x0010 (H)
Copyright 2004, IC Media Corporation
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Page 27
9/22/2004