IA4420 Datasheet, PDF (18/29 Pages) List of Unclassifed Manufacturers – Universal ISM Band FSK Transceiver

IA4420
8. Receiver FIFO Read Command
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1011000000000000
PO R
B0 0 0 h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
nSEL
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SDI
SDO
FFIT in RX mode / RGIT otherwise
received bits out
MSB
LSB
Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command
9. AFC Command
Bit 15 14 13 12 11 10 9
1100010
876543
0 a1 a0 rl1 rl0 st
210
fi oe en
POR
C4F7h
Bit 7-6 (a1 to a0): Automatic operation mode selector:
a1 a0
0
0 Auto mode off (Strobe is controlled by microcontroller)
0
1 Runs only once after each power-up
1
0
Keep the f_offset only during receiving (VDI=high)
1
1
Keep the f_offset value independently from the state of the VDI signal
Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
rl1 rl0
00
01
10
11
Max deviation
No restriction
+15 f_res to -16 f_res
+7 f_res to -8 f_res
+3 f_res to -4 f_res
f_res:
315, 433 MHz bands: 2.5 kHz
868 MHz band: 5 kHz
915 MHz band: 7.5 kHz
Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block.
Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement
uncertainty is about the half.
Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.
18