IA4420 Datasheet, PDF (11/29 Pages) List of Unclassifed Manufacturers – Universal ISM Band FSK Transceiver

IA4420
CONTROL INTERFACE
Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK
whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command
code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no
influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
· The TX register is ready to receive the next byte (RGIT)
· The FIFO has received the preprogrammed amount of bits (FFIT)
· Power-on reset (POR)
· FIFO overflow (FFOV) / TX register underrun (RGUR)
· Wake-up timer timeout (WKUP)
· Negative pulse on the interrupt input pin nINT (EXT)
· Supply voltage below the preprogrammed value is detected (LBD)
FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify
the source of the IT, the status bits should be read out.
Timing Specification
Symbol
tCH
tCL
tSS
tSH
tSHI
tDS
tDH
tOD
tBL
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
Push-button input low time
Minimum Value [ns]
25
25
10
10
25
5
5
10
25
Timing Diagram
nSEL
SCK
SDI
t_SS
t_CH
t_CL
t_DS
t_DH
BIT 15
BIT 14
BIT 13
t_OD
BIT 8
BIT 7
t_SHI
t_SH
BIT 1
BIT 0
SDO
FFIT
FFOV
CRL
ATS
OFFS(0)
FIFO OUT
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