IA4420 Datasheet, PDF (12/29 Pages) List of Unclassifed Manufacturers – Universal ISM Band FSK Transceiver

IA4420
Control Commands
Control Command
1 Configuration Setting Command
2 Power Management Command
3 Frequency Setting Command
4 Data Rate Command
5 Receiver Control Command
6 Data Filter Command
7 FIFO and Reset Mode Command
8 Receiver FIFO Read Command
9 AFC Command
10 TX Configuration Control Command
11 Transmitter Register Write Command
12 Wake-Up Timer Command
13 Low Duty-Cycle Command
14
Low Battery Detector and Microcontroller
Clock Divider Command
15 Status Read Command
Related Parameters/Functions
Frequency band, crystal oscillator load capacitance,
baseband filter bandwidth, etc.
Receiver/Transmitter mode change, synthesizer, xtal
osc, PA, wake-up timer, clock output can be enabled
here
Data frequency of the local oscillator/carrier signal
Bit rate
Function of pin 16, Valid Data Indicator, baseband bw,
LNA gain, digital RSSI threshold
Data filter type, clock recovery parameters
Data FIFO IT level, FIFO start control, FIFO enable and
FIFO fill enable
RX FIFO can be read with this command
AFC parameters
Modulation parameters, output power, ea
TX data register can be written with this command
Wake-up time period
Enable low duty-cycle mode. Set duty-cycle.
LBD voltage and microcontroller clock division ratio
Status bits can be read out
Related control bits
el, ef, b1 to b0, x3 to x0
er, ebb, et, es, ex, eb, ew, dc
f11 to f0
cs, r6 to r0
p16, d1 to d0, i2 to i0, g1 to g0, r2 to
r0
al, ml, s1 to s0, f2 to f0
f3 to f0, s1 to s0, ff, fe
a1 to a0, rl1 to rl0, st, fi, oe, en
mp, m3 to m0, p2 to p0
t7 to t0
r4 to r0, m7 to m0
d6 to d0, en
d2 to d0, v4 to v0
In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the
command registers after power-on.
Description of the Control Commands
1. Configuration Setting Command
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0
POR
8008h
Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level.
Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.
b1 b0
00
01
10
11
Frequency Band {MHz]
315
433
868
915
x3 x2 x1 x0
0000
0001
0010
0011
1110
1111
Crystal Load Capacitance [pF]
8.5
9.0
9.5
10.0
…
15.5
16.0
12