L64105 Datasheet, PDF (99/454 Pages) List of Unclassifed Manufacturers – AUDIO/VIDEO DECODER

Setting the Channel Bypass Enable bit (bit 3 in Register 5 - page 4-10)
allows the host to write data directly to the video channel through this
register, bypassing the parallel channel input port.
Figure 4.16 Register 29 (0x01D) Audio Channel Bypass Data [7:0]
7
0
Audio Channel Bypass Data [7:0]
W
Setting the Channel Bypass Enable bit (bit 3 in Register 5 - page 4-10)
allows the host to write data directly to the audio channel through this
register, bypassing the parallel channel input port.
Registers 30–63 Reserved
[7:0]
4.2 Video Decoder Registers
Figure 4.17 Register 64 (0x040)
7
5
Reserved
4
2
Aux Data Layer ID [2:0]
1
0
Aux Data FIFO Status [1:0]
R
Read Only
Reset Aux
Data FIFO
W
Aux Data FIFO Status [1:0]
R [1:0]
The states of these bit indicate the status of the Aux Data
FIFO as shown in the following table. Once “overrun”
(0b11) occurs, the status stays at overrun until the
register is read.
Bits
0b00
0b01
0b10
0b11
Status
Empty
Data ready
Full
Overrun
Reset Aux Data FIFO
W0
Writing a 1 to this bit resets the Aux Data FIFO to empty.
Any data in the FIFO at this time is lost.
Video Decoder Registers
4-17