L64105 Datasheet, PDF (280/454 Pages) List of Unclassifed Manufacturers – AUDIO/VIDEO DECODER

8.5.2 Repeat Frame
The repeat frame feature is controlled by two bits in Register 237
(page 4-51). When the host clears the Video Continuous Repeat Frame
Mode bit (bit 1) and sets the Video Repeat Frame Enable bit (bit 0), the
Video Encoder repeats the last field of the frame currently being decoded
twice. That is, its first field is displayed once and its last field is displayed
three times in succession. This is shown in Figure 8.6. After the Video
Encoder accepts the command, it automatically clears the Video Repeat
Frame Enable bit.
If the host sets both bits, the last field of the frame being decoded is
continuously repeated and the Video Decoder is paused. If the repeat
lasts over several frames, the Video ES Channel Buffer could overflow
unless it also is paused or stopped by the host.
Note:
Since the Video Decoder is paused, picture start code
interrupts are not generated and no data is read into the
Auxiliary Data FIFO during the repeats.
The host can stop the repeat by clearing either or both bits. If it clears
the continuous mode bit only, the field is repeated two more times and
the Video Decoder clears the repeat mode bit. If the host clears the
repeat enable bit only, the currently displayed frame is completed (by
repeating the last field one more time, if necessary) and the next
decoded frame is displayed.
If only one field is repeated, the fields are then out of sync with the
even/odd interlacing. This condition is automatically corrected if the host
sets the Automatic Field Inversion Correction bit in Register 279
(page 4-65).
8-38
Video Decoder Module