L64105 Datasheet, PDF (110/454 Pages) List of Unclassifed Manufacturers – AUDIO/VIDEO DECODER

Figure 4.35 Registers 108–110 (0x06C–0x06E) Video ES Channel Buffer Compare
DTS Address [18:0]
7
Reg. 108
LSB
Reg. 109
Reg. 110
MSB
3
2
0
Video ES Channel Buffer Compare DTS Address [7:0]
Write
Video ES Channel Buffer Compare DTS Address [15:8]
Write
Reserved
Video ES Channel Buffer Compare
DTS Address [18:16]
Write
The host can write a Video ES channel buffer address in these registers
to be compared with the current read pointer address of the Video ES
channel buffer. When the current read pointer address matches the
contents of the registers and the chip is in the Video Read Compare
Mode (Register 69, bit 0 set, page 4-21), the DTS Video Event Interrupt
bit (Register 2, bit 7, page 4-6) is set and, if the interrupt is not masked,
the INTRn output signal is asserted.
This can be used by the host as an aid to audio/video synchronization.
When INTRn is asserted, the host should read Registers 0 through 4 to
determine the cause of the interrupt, take the necessary action, and
deassert INTRn by setting the Clear Interrupt Pin bit (Register 6, bit 0,
page 4-10).
Figure 4.36 Registers 111–113 (0x06F–0x071) Audio ES Channel Buffer Read
Address [19:0]
Reg. 111
LSB
Reg. 112
Reg. 113
MSB
7
4
3
0
Audio ES Channel Buffer Read Address [7:0]
Read Only
Audio ES Channel Buffer Read Address [15:8]
Read Only
Reserved
Audio ES Channel Buffer Read Address [19:16]
Read Only
These registers contain the current read pointer address of the Audio ES
channel buffer. The LSB should be read first. since this captures the next
significant byte and MSB in Registers 112 and 113. These should then
be read immediately to ensure that the correct captured value is read.
When set, the most significant bit (bit 3 of Register 113) indicates that
the read pointer has wrapped around from the end address to the start
address of the buffer.
4-28
Register Descriptions