L64105 Datasheet, PDF (127/454 Pages) List of Unclassifed Manufacturers – AUDIO/VIDEO DECODER

Internal SDRAM State [2:0]
R [5:3]
Used to monitor the internal SDRAM state (diagnostics
only).
Bits [5:3]
0b000
0b001
0b010
0b011
0b100
0b101
Description
Waiting for 2 clocks to reach synchronization
SDRAM initialization (precharge both banks)
SDRAM Initialization (first 8 refreshes)
SDRAM Initialization (set mode register)
SDRAM Initialization (second 8 refreshes)
SDRAM ready to operate
Reserved
[7:6]
Figure 4.62 Register 206 (0x0CE)
7
6
Internal Phase State
(current cycle) [1:0]
Read Only
5
4
Internal Phase State
(1 cycle before) [1:0]
Read Only
3
2
Internal Phase State
(2 cycles before) [1:0]
Read Only
1
0
Internal Phase State
(3 cycles before) [1:0]
Read Only
When the two internal clocks reach synchronization, the internal phase
state should be looping through states 01, 10, and 11. If a 00 state is
ever reached, it indicates that the synchronization has been lost. These
registers are used for diagnostic purposes only.
Figure 4.63 Registers 207–212 (0x0CF–0x0D4)
7
0
Reg. 207
LSB
Phase Detect Test High Freq [7:0]
R/W
Reg. 208
MSB
Phase Detect Test High Freq [15:8]
R/W
Reg. 209
LSB
Phase Detect Test Low Freq [7:0]
R/W
Reg. 210
MSB
Phase Detect Test Low Freq [15:8]
R/W
Reg. 211
LSB
VCO Test High Freq [7:0]
R/W
Reg. 212
MSB
VCO Test High Freq [15:8]
R/W
Memory Interface Registers
4-45