W3150 Datasheet, PDF (9/59 Pages) List of Unclassifed Manufacturers – WIZnet’s Online Technical Support

1.1. MII Signal Description
Pin#
55
53
52
51
50
49
46
48
47
44
43
42
41
40
Signal
TXC
TXEN
TXD[3]
TXD[2]
TXD[1]
TXD[0]
RXC
COL
CRS
RXDV
RXD[3]
RXD[2]
RXD[1]
RXD[0]
I/O
Description
Transmit Clock
This pin provides a continuous clock as a timing reference for TXD[3:0] and
I
TXEN. TXC is sourced by the PHY. TXC is 2.5 MHz in 10BASET Nibble
mode, and 25 MHz in 100BASETX Nibble mode.
Transmit Enable
This output signal indicates the presence of a valid nibble data on TXD[3:0]. It
becomes active when the first nibble data of the packet is valid on TXD[3:0]
O
and goes low after the last nibble data of the packet is clocked out of
TXD[3:0]. This signal connects directly to the PHY device. This signal is active
high.
Transmit Data
These pins provide Nibble NRZ data to the PHY synchronously with TXC
O
when TXEN is asserted.
Receive Clock
This pin provides a continuous clock reference for RXDV and RXD[3:0]
I
signals. RXC is sourced by the PHY. RXC is 2.5 MHz in 10BASET Nibble
mode, and 25 MHz in 100BASETX Nibble mode.
Collision Detect
This pin becomes active when a collision has been detected in Half Duplex
I
modes. This signal is asynchronous, active high and ignored during full-
duplex operation. This signal is active high.
Carrier Sense
I
This pin indicates that carrier is present. This signal is active high.
Receive Data Valid
This signal is asserted high when received data is present on the RXD[3:0]
I
pins; the signal is deasserted at the end of the packet. The signal is valid on
the rising of the RXC.
Receive Data
These pins receive Nibble NRZ data from the PHY device synchronously with
I
RXC when RXDV is asserted.
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