W3150 Datasheet, PDF (50/59 Pages) List of Unclassifed Manufacturers – WIZnet’s Online Technical Support

0x01
0x02
0x03
IDM_AR0
IDM_AR1
IDM_DR
Indirect bus I/F mode address Register
MSB/LSB can be decided by LB bit of MODE Register.
1. In case that LB bit is set to 0
0x01
0x02
IDM_AR0 : MSB
IDM_AR1 : LSB
2. In case that LB bit is set to 1
0x01
0x02
IDM_AR0 : LSB
IDM_AR1 : MSB
Indirect bus I/F mode data Register
In order to read or write the internal register or internal TX/RX Memory,
1. Write the address to read or write on IDM_AR0,1.
2. Read or Write IDM_DR.
In order to read or write the data on the sequential address, set AI bit of MR(Mode Register). With this, user
performs above 1 only one time. Whenever reading or writing IDM_DR, IDM_AR value increases by 1
automatically. So, the value can be processed on the sequential address just by continuous reading or
writing of IDM_DR.
6.3. MII (Media Independent Interface)
The MII handles the data transfer between the W3150 and the Physical Layer Device.
The MII is composed of TX_CLK, TXE, and TXD[0:3] signals for sending data and RX_CLK, CRS, RXDV,
RXD[0:3], and COL signals for receiving data.
When sending data from the W3150, TXE and TXD[0:3] are output in synchronization with the falling edges
of TX_CLK input from the Physical Layer Device because Physical Layer Devices generally recognize the
rising edges of TX_CLK.
When receiving data, in general, the Physical Layer Devices output CRS, RXDV, RXD[0:3], and COL signals
in synchronization with the falling edges of RX_CLK, so the W3100A recognizes the signals at the rising
edges of RX_CLK.
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