GS82032T Datasheet, PDF (9/23 Pages) List of Unclassifed Manufacturers – 64K x 32 2M Synchronous Burst SRAM

Preliminary
GS82032T/Q-150/138/133/117/100/66
Absolute Maximum Ratings
(All voltages reference to V_SS)
Symbol
Description
Value
Unit
V_DD
V_DDQ
V_CK
V_I/O
V_IN
I_IN
I_OUT
P_D
T_STG
T_BIAS
Voltage on V_DD Pins
Voltage in V_DDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
Temperature Under Bias
–0.5 to 4.6
V
–0.5 to V_DD
V
–0.5 to 6
V
–0.5 to V_DDQ+0.5 (≤ 4.6 V max.)
V
–0.5 to V_DD+0.5 (≤ 4.6 V max.)
V
+/–20
mA
+/–20
mA
1.5
W
–55 to 125
o_C
–55 to 125
o_C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be
restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings,
for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Symbol Min.
Typ.
Max.
Unit Notes
Supply Voltage
V_DD
3.135
3.3
3.6
V
I/O Supply Voltage
V_DDQ
2.375
2.5
V_DD
V
1
Input High Voltage
V_IH
1.7
—
V_DD +0.3
V
2
Input Low Voltage
V_IL
–0.3
—
0.8
V
2
Ambient Temperature (Commercial Range Versions)
T_A
0
25
70
°C
3
Ambient Temperature (Industrial Range Versions)
T_A
–40
25
85
°C
3
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V_DDQ ≤ 2.375 V (i.e., 2.5 V I/O)
and 3.6 V ≤ V_DDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < V_DD+2 V with a pulse width not to exceed 20% tKC.
Rev: 1.04 2/2001
9/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.