GS82032T Datasheet, PDF (6/23 Pages) List of Unclassifed Manufacturers – 64K x 32 2M Synchronous Burst SRAM

Preliminary
GS82032T/Q-150/138/133/117/100/66
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key⁵
E1
E^{2 ADSP ADSC ADV} W³ DQ⁴
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
None
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
X
H
X
X
L
X
X High-Z
X
L
F
L
X
X
X High-Z
X
L
F
H
L
X
X High-Z
R
L
T
L
X
X
X
Q
R
L
T
H
L
X
F
Q
W
L
T
H
L
X
T
D
CR
X
X
H
H
L
F
Q
CR
H
X
X
H
L
F
Q
CW
X
X
H
H
L
T
D
CW
H
X
X
H
L
T
D
X
X
H
H
H
F
Q
H
X
X
H
H
F
Q
X
X
H
H
H
T
D
H
X
X
H
H
T
D
Notes:
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.04 2/2001
6/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.