GS82032T Datasheet, PDF (11/23 Pages) List of Unclassifed Manufacturers – 64K x 32 2M Synchronous Burst SRAM

Preliminary
GS82032T/Q-150/138/133/117/100/66
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
2. 3V
0.2 V
1 V/ns
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t_LZ, t_HZ, t_OLZ and t_OHZ.
4. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
Output Load 2
2.5 V
50Ω
30pF^*
DQ
225Ω
VT = 1.25 V
* Distributed Test Jig Capacitance
5pF^{* 225Ω}
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
ZZ Input Current
Symbol
I_IL
I_INZZ
Mode Pin Input Current
I_INM
Output Leakage Current
I_OL
Output High Voltage
V_OH
Output High Voltage
V_OH
Output Low Voltage
V_OL
Test Conditions
V_IN = 0 to V_DD
V_DD ≥ V_IN ≥ V_IH
0 V ≤ V_IN ≤ V_IH
V_DD ≥ V_IN ≥ V_IL
0 V ≤ V_IN ≤ V_IL
Output Disable,
V_OUT = 0 to V_DD
I_OH = –4 mA, V_DDQ = 2.375 V
I_OH = –4 mA, V_DDQ = 3.135 V
I_OL = 4 mA
Min
–1 uA
–1 uA
–1 uA
–300 uA
–1 uA
–1 uA
1.7 V
2.4 V
Max
1 uA
1 uA
300 uA
1 uA
1 uA
1 uA
0.4 V
Rev: 1.04 2/2001
11/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.