GS82032T Datasheet, PDF (7/23 Pages) List of Unclassifed Manufacturers – 64K x 32 2M Synchronous Burst SRAM

Simplified State Diagram
Preliminary
GS82032T/Q-150/138/133/117/100/66
X
Deselect
W
R
W
R
X
First Write ^R
CW
CR
First Read
X
CR
W
R
X Burst Write
CR
CW
R
Burst Read
X
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.04 2/2001
7/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.