GS82032T Datasheet, PDF (18/23 Pages) List of Unclassifed Manufacturers – 64K x 32 2M Synchronous Burst SRAM

Preliminary
GS82032T/Q-150/138/133/117/100/66
Pipelined SCD Read-Write Cycle Timing
CK
ADSP
ADSC
ADV
A0–An
GW
BW
BA–BWD
E1
E2
E3
G
DQa–DQd
Single Read
Single Write
tKL
Burst Read
tS tH
tKH
tKC
ADSP is blocked by E inactive
tS tH _{ADSC initiated read}
tS tH
tS _tH
RD1
tS tH
WR1
RD2
tS
tH
tS tH
tS tH
tS tH
tS tH
WR1
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
Deselected with E3
tOE tOHZ
tS tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2B
Q2C Q2D
Rev: 1.04 2/2001
18/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.