EN29F800 Datasheet, PDF (9/38 Pages) List of Unclassifed Manufacturers – 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 5.0 Volt-only

EN29F800
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low V_CC Write Inhibit
When Vcc is less than V_LKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than V_LKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
V_LKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE , CE or W E do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of CE = V_IH, or W E = V_IH. To initiate a write cycle,
CE and W E must be a logical zero. If CE , W E , and OE are all logical zero (not
recommended usage), it will be considered a write.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE = V_IL, W E = V_IL and OE = V_IH, the device will not accept commands on the rising edge of
WE.
4800 Great America Parkway, Suite 202
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Santa Clara, CA 95054
Rev. E, Issue Date: 2001/07/05
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