BC41B143A-DS-002PD Datasheet, PDF (80/89 Pages) List of Unclassifed Manufacturers – BlueCore 4-ROM CSP EDR Single Chip Bluetooth v2.0 + EDR System

Device Terminal Descriptions
11.11.2 Status after Reset
The state of the IC after a reset is as follows:
! Warm Reset⁽¹⁾: Baud rate and RAM data typically remain available, depending on firmware
configuration
! Cold Reset⁽²⁾: Baud rate and RAM data not available
Note:
(1)
(2)
Warm Reset preserves persistent store in RAM but otherwise does a full system reset. All of memory
(except the PS RAM) is erased. The memory manager is reinitialised. All the hardware is reset, all
Bluetooth links are lost, and the USB bus is detached from and reattached to.
Cold Reset is one of the following:
! Power cycle
! System reset (firmware fault code)
! Reset signal, see Section 11.11.
11.12 Power Supply
11.12.1 Voltage Regulator
An on-chip linear voltage regulator can be used to power the 1.8V dependent supplies. It is advised that a
smoothing circuit using a 2.2μF low ESR capacitor in series with a 2.2Ω resistor is placed on the output
VDD_ANA.
The regulator is switched into a low power mode when the device is sent into deep sleep mode. When the
on-chip regulator is not required VDD_ANA is used as a 1.8V input and VREG_IN must be either open circuit or
tied to VDD_ANA.
11.12.2 Sequencing
It is recommended that VDD_CORE, VDD_RADIO and VDD_VCO are powered at the same time. This is true
when these supplies are powered from the internal regulator in BlueCore4-ROM CSP. The order of powering
supplies for VDD_PIO, VDD_PADS and VDD_USB is not important. However, if VDD_CORE is not present all
inputs have a weak pull-down irrespective of the reset state.
11.12.3 Sensitivity to Disturbances
It is recommended that if BlueCore4-ROM CSP is supplied from an external voltage source VDD_VCO,
VDD_ANA and VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz. Single tone
frequencies are also to be avoided. A simple RC filter is recommended for VDD_CORE as this reduces transients
put back onto the power supply rails.
The transient response of the regulator is also important as at the start of a packet power consumption will jump
to the levels defined in peak current consumption section. It is essential that the power rail recovers quickly, so
the regulator should have a response time of 20μs or less.
See Figure 12.1, the application schematic.
BC41B143A-ds-002Pd
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 80 of 89