BC41B143A-DS-002PD Datasheet, PDF (69/89 Pages) List of Unclassifed Manufacturers – BlueCore 4-ROM CSP EDR Single Chip Bluetooth v2.0 + EDR System

BlueCore4-ROM
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
Device Terminal Descriptions
Upto 2048kHz
8kHz
Figure 11.18: BlueCore4-ROM CSP as PCM Interface Slave
11.7.2 Long Frame Sync
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or
samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When
BlueCore4-ROM CSP is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC
is 8 bits long. When BlueCore4-ROM CSP is configured as PCM Slave, PCM_SYNC can be from two
consecutive falling edges of PCM_CLK to half the PCM_SYNC rate, that is 62.5μs long.
PCM_SYNC
PCM_CLK
PCM_OUT
1
2
3
4
5
6
78
PCM_IN
Undefined
1
2
3
4
56
7
8 Undefined
Figure 11.19: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore4-ROM CSP samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising
edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position
or on the rising edge.
11.7.3 Short Frame Sync
In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always
one clock cycle long.
PCM_SYNC
PCM_CLK
PCM_OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PCM_IN Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Undefined
Figure 11.20: Short Frame Sync (Shown with 16-bit Sample)
BC41B143A-ds-002Pd
This material is subject to CSR’s non-disclosure agreement
Production Information
© Cambridge Silicon Radio Limited 2005
Page 69 of 89