BC352239A Datasheet, PDF (70/116 Pages) List of Unclassifed Manufacturers – BlueCore 3-Multimedia External

Device Terminal Descriptions
8.6.9 USB 1.1 Compliance
BlueCore3-Multimedia External is qualified to the USB specification v1.1, details of which are available from
http://www.usb.org. The specification contains valuable information on aspects such as PCB track impedance,
supply inrush current and product labelling.
Although BlueCore3-Multimedia External meets the USB specification, CSR cannot guarantee that an application
circuit designed around the chip is USB compliant. The choice of application circuit, component choice and PCB
layout all affect USB signal quality and electrical characteristics. The information in this document is intended as
a guide and should be read in association with the USB specification, with particular attention being given to
Chapter 7. Independent USB qualification must be sought before an application is deemed USB compliant and
can bear the USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test
house.
Terminals USB_DP and USB_DN adhere to the USB specification 2.0 (Chapter 7) electrical requirements.
8.6.10 USB 2.0 Compatibility
BlueCore3-Multimedia External is compatible with USB v2.0 host controllers; under these circumstances the two
ends agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
8.7 Serial Peripheral Interface
BlueCore3-Multimedia External uses 16-bit data and 16-bit address serial peripheral interface, where
transactions may occur when the internal processor is running or is stopped. This section details the
considerations required when interfacing to BlueCore3-Multimedia External via the four dedicated serial
peripheral interface terminals. Data may be written or read one word at a time or the auto increment feature may
be used to access blocks.
8.7.1 Instruction Cycle
The BlueCore3-Multimedia External is the slave and receives commands on SPI_MOSI and outputs data on
SPI_MISO. The instruction cycle for a SPI transaction is shown in Table 8..
1 Reset the SPI interface
2 Write the command word
3 Write the address
4 Write or read data words
5 Termination
Hold SPI_CSB high for two SPI_CLK cycles
Take SPI_CSB low and clock in the 8 bit command
Clock in the 16-bit address word
Clock in or out 16-bit data word(s)
Take SPI_CSB high
Table 8.19: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into
the BlueCore3-Multimedia External on the rising edge of the clock line SPI_CLK. When reading,
BlueCore3-Multimedia External will reply to the master on SPI_MISO with the data changing on the falling edge
of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is teminated by taking SPI_CSB
high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this
BlueCore3-Multimedia External offers increased data transfer efficiency via an auto increment operation. To
invoke auto increment, SPI_CSB is kept low, which auto increments the address, while providing an extra 16
clock cycles for each extra word to be written or read.
BC352239A-ds-001Pc
© Cambridge Silicon Radio Limited 2004
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