SI5010 Datasheet, PDF (7/16 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Si5010
Table 3. AC Characteristics (Clock & Data)
(V_A 2.5 V ± 5%, T_A = –40°C to 85°C)
Parameter
Output Clock Rate
Output Rise Time
Output Fall Time
Clock to Data Delay
OC-12
OC-3
Input Return Loss
Symbol
f_CLK
t_R
t_F
t_(c-d)
Test Condition
Figure 4
Figure 4
Figure 3
100 kHz–622 MHz
Min Typ Max Unit
.15
—
666 MHz
—
100
TBD
ps
—
100
TBD
ps
—
890
TBD
ps
—
4100 TBD
ps
18.7
—
—
dB
Table 4. AC Characteristics (PLL Characteristics)
(V_DD = 2.5 V ± 5%, T_A = –40°C to 85°C)
Parameter
Jitter Tolerance (OC-12 Mode)^*
Symbol
J_TOL(PP)
Test Condition
f = 30 Hz
f = 300 Hz
Min
Typ
Max
40
TBD
—
4
TBD
—
f = 25 kHz
4
TBD
—
Jitter Tolerance (OC-3 Mode)^*
J_TOL(PP)
f = 250 kHz
f = 30 Hz
f = 300 Hz
0.4 TBD
—
40
TBD
—
4
TBD
—
f = 6.5 kHz
4
TBD
—
f = 65 kHz
0.4 TBD
—
RMS Jitter Generation^*
J_GEN(RMS) with no jitter on serial data —
1.6
3.0
Peak-to-Peak Jitter Generation
J_GEN(PP) with no jitter on serial data —
25
55
Jitter Transfer Bandwidth^*
J_BW
OC-12 Mode
—
—
500
OC-3 Mode
—
—
130
Jitter Transfer Peaking^*
J_P
f < 2 MHz
—
.03
0.1
Acquisition Time
T_AQ
After falling edge of
1.45
1.5
1.7
PWRDN/CAL
From the return of valid
40
data
60
150
Input Reference Clock Duty Cycle
Reference Clock Range
C_DUTY
40
50
60
19.44
155.52
Input Reference Clock Frequency
Tolerance
C_TOL
–100
—
100
Frequency Difference at which
LOL
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
TBD 600 TBD
Frequency Difference at which
LOCK
TBD 300
Receive PLL goes into Lock
(REFCLK compared to the divided
down VCO clock)
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 2²³ –1 data pattern.
TBD
Unit
UI_PP
UI_PP
UI_PP
UI_PP
UI_PP
UI_PP
UI_PP
UI_PP
mUI
mUI
kHz
kHz
dB
ms
µs
%
MHz
ppm
ppm
ppm
Preliminary Rev. 0.31
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