SI5010 Datasheet, PDF (11/16 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Si5010
Differential Input Circuitry
Differential Output Circuitry
The Si5010 provides differential inputs for both the high
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 8. In applications where direct DC
coupling is possible, the 0.1 µF capacitors may be
omitted. The DIN and REFCLK input amplifiers require
an input signal with a minimum differential peak-to-peak
voltage listed in Table 2 on page 6.
The Si5010 utilizes a current mode logic (CML)
architecture to output both the recovered clock
(CLKOUT) and data (DOUT). An example of output
termination with AC coupling is shown in Figure 9. In
applications in which direct DC coupling is possible, the
0.1 µF capacitors may be omitted. The differential
peak-to-peak voltage swing of the CML architecture is
listed in Table 2 on page 6.
Differential
Driver
0.1 µ F
Zo = 50 Ω
Si5010
D IN + ,
REFCLK+
2.5 kΩ
VDD
0.1 µ F
Zo = 50 Ω
D IN – ,
REFCLK–
10 kΩ
2.5 kΩ
10 kΩ
102Ω
GND
Figure 8. Input Termination for DIN and REFCLK (AC Coupled)
Si5010
VDD
100 Ω
DOUT+,
CLKOUT+
0.1 µ F
VDD
50 Ω
Zo = 50 Ω
DOUT–,
CLKOUT–
0.1 µ F
Zo = 50 Ω
100 Ω
VDD
50 Ω
VDD
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
Preliminary Rev. 0.31
11