SI5010 Datasheet, PDF (13/16 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Pin #
12, 13
15
16, 17
19
20
Si5010
Table 8. Si5010 Pin Descriptions (Continued)
Pin Name
I/O Signal Level
Description
DOUT–,
O
DOUT+
PWRDN/CAL
I
CML
LVTTL
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
Power Down.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a
high-to-low transition on this pin. (See "PLL
Self-Calibration" on page 9.)
Note: This input has a weak internal pulldown.
CLKOUT–,
O
CLKOUT+
RATESEL
I
NC
CML
LVTTL
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Note: This input has a weak internal pulldown.
No Connect.
This pin should be tied to ground.
Preliminary Rev. 0.31
13