SI5010 Datasheet, PDF (10/16 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Si5010
Sinusoidal
Input
Jitter (UI p-p)
15
1.5
0.15
Slope = 20 dB /Decade
Jitter
Transfer
0.1 dB
Acceptable
Range
20 dB/Decade
Slope
f0
f1
f2
f3
ft
Frequency
Fc
Frequency
SONET
Data Rate
OC-12
OC-3
F0
(Hz)
10
10
F1
(Hz)
30
30
F2 F3 Ft
(Hz) (kHz) (kHz)
300 25
250
300 6.5
65
Figure 6. Jitter Tolerance Specification
SONET
Data Rate
OC-12
OC-3
Fc
(kHz)
500
130
Figure 7. Jitter Transfer Specification
Jitter Transfer
The Si5010 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 7). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 6.
Jitter Generation
The Si5010 meets all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5010 typically generates less than 1.6 mUI_RMS of jitter
when presented with jitter-free input data.
Power Down
The Si5010 provides a power down pin, PWRDN/CAL,
that disables the device. When the PWRDN/CAL pin is
driven “high”, the positive and negative terminals of
CLKOUT and DOUT are each tied to VDD through
100 Ω on-chip resistors. This feature is useful in
reducing power consumption in applications that
employ redundant serial channels. When PWRDN/CAL
is released (set to “low”) the digital logic resets to a
known initial condition, recalibrates the DSPLL, and will
begin to lock to the data stream.
Note: LOL is not asserted when the device is in the power
down state.
Device Grounding
The Si5010 uses the GND pad on the bottom of the
20-pin micro leaded package (MLP) for device ground.
This pad should be connected directly to the analog
supply ground. See Figures 10 and 11 for the ground
(GND) pad location.
Bias Generation Circuitry
The Si5010 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
10
Preliminary Rev. 0.31