OV9625 Datasheet, PDF (7/30 Pages) List of Unclassifed Manufacturers – OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP

Omni ision
Functional Description
Timing Generator
In general, the timing generator controls the following
functions:
• Frame Exposure Mode Timing
• Frame Rate Timing
• Frame Rate Adjust
Frame Exposure Mode Timing
OV9625/OV9121 supports frame exposure mode.
Typically the frame exposure mode must work with the aid
of an external shutter.
The frame exposure pin, FREX (pin 8) is the frame
exposure mode enable pin and EXPSTB (pin 12) serves
as the exposure start trigger for the sensor. There are two
ways to set Frame Exposure mode:
• Control both FREX and EXPSTB pins - Frame
Exposure mode can be set by pulling both FREX and
EXPSTB pins high at the same time (see Figure 19).
• Control FREX only and keep EXPSTB low - In this
case, the pre-charge time is tline and sensor
exposure time is the period after pre-charge until the
shutter closes (see Figure 18).
When the external master device asserts the FREX pin
high, the sensor array is quickly pre-charged and stays in
reset mode until the EXPSTB pin is pulled low by the
external master (sensor exposure time can be defined as
the period between EXPSTB low to shutter close). After
the FREX pin is pulled low, the video data stream is then
clocked to the output port in a line-by-line manner. After
completing one frame of data output, OV9625/OV9121
will output continuous live video data unless in single
frame transfer mode. Figure 18 and Figure 19 show the
detailed timing for this mode.
For frame exposure, register AEC (0x10) must be set to
0xFF and register GAIN (0x00) should be no larger than
0x10 (maximum 2x gain).
Frame Rate Timing
Default frame timing is illustrated in Figure 16 and
Figure 17. Refer to Table 2 for the actual pixel rate at
different frame rates.
Table 2
Frame and Pixel Rates
Frame Rage (fps) 15 10 7.5 6
5
PCLK (MHz)
24 16 12 9.6 8
NOTE: Based on 24 MHz external clock and internal PLL
on, frame rate is adjusted by the main clock divide method.
Frame Rate Adjust
OV9625/OV9121 offers three methods of frame rate
adjustment.
1. Clock prescaler (see “CLKRC” on page 20)
By changing the system clock divide ratio, the frame
rate and pixel rate will change together. This
method can be used for dividing the frame/pixel rate
by: 1/2, 1/3, 1/4 … 1/64 of the input clock rate.
2. Line adjustment (see “COML” on page 24 and see
“FRARL” on page 25)
By adding dummy pixel timing in each line, the
frame rate can be changed while leaving the pixel
rate as is.
3. Vertical sync adjustment
By adding dummy line periods to the vertical sync
period (see “ADDVSL” on page 25 and see
“ADDVSH” on page 25), the frame rate can be
altered while the pixel rate remains the same.
After changing registers COML (0x2A) and FRARL (0x2B)
to adjust the dummy pixels, it is necessary to write to
register COMH (0x12) or CLKRC (0x11) to reset the
counter. Generally, OmniVision suggests users write to
register COMH (0x12) (to change the sensor mode) as the
last one. However, if you want to adjust the cropping
window, it is necessary to write to those registers after
changing register COMH (0x12). To use COMH to reset
the counter, it is necessary to generate a pulse on
resolution control register bit COMH[6].
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
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