OV9625 Datasheet, PDF (20/30 Pages) List of Unclassifed Manufacturers – OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP

OV9625/OV9121 CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni ision
Table 11
Address
(Hex)
11
Device Control Register List
Register
Name
CLKRC
Default
(Hex)
00
R/W
Description
Clock Rate Control
Bit[7]: Internal PLL ON/OFF selection
0: PLL disabled
1: PLL enabled
RW
Bit[6]: Digital video port master/slave selection
0: Master mode, sensor provides PCLK
1: Slave mode, external PCLK input from XCLK1 pin
Bit[5:0]: Clock divider
CLK = XCLK1/(decimal value of CLKRC[5:0] + 1)
Common Control H
Bit[7]: SRST
1: Initiates soft reset. All register are set to factory
default values after which the chip resumes normal
operation
Bit[6]: Resolution selection
0: SXGA
1: VGA
Bit[5]: Average luminance value pixel counter ON/OFF
12
COMH
20
RW
Bit[4]:
0: OFF
1: ON
Reserved
Bit[3]: Master/slave selection
Bit[2]:
0: Master mode
1: Slave mode
Window output selection
0: Output only pixels defined by window registers
1: Output all pixels
Bit[1]: Color bar test pattern
0: OFF
1: ON
Bit[0]: Reserved
20
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003