OV9625 Datasheet, PDF(6/30 Page) List of Unclassifed Manufacturers – OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP

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OV9625 Datasheet, PDF (6/30 Pages) List of Unclassifed Manufacturers – OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP

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OV9625/OV9121 CMOS SXGA (1.3 MPixel) CAMERACHIPâ¢

Omni ision

Digital Video Port

MSB/LSB Swap

OV9625/OV9121 has a 10-bit digital video port. The MSB

and LSB can be swapped with the control registers.

Figure 11 shows some examples of connections with

external devices.

Figure 11 Connection Examples

MSB D9

LSB D0

OV9625

(OV9121)

External

Device

Default 10-bit Connection

LSB D9

MSB D0

OV9625

(OV9121)

External

Device

Swap 10-bit Connection

MSB D9

LSB D0

OV9625

(OV9121)

External

Device

Default 8-bit Connection

LSB D9

MSB D0

OV9625

(OV9121)

External

Device

Swap 8-bit Connection

Line/Pixel Timing

The OV9625/OV9121 digital video port can be

programmed to work in either master or slave mode.

In both master and slave modes, pixel data output is

synchronous with PCLK (or MCLK if port is a slave),

HREF and VSYNC. The default PCLK edge for valid data

is the negative edge but may be programmed with register

COMK[4] (see âCOMKâ on page 22) for the positive edge.

Basic line/pixel output timing is illustrated in Figure 14 and

Figure 15.

To minimize image capture circuitry and conserve

memory space, PCLK output can be programmed with

qualified by the active video period as defined by the

HREF signal. See Figure 12 for details.

Figure 12 PCLK Output Only at Valid Pixels

PCLK

PCLK active edge negative

HREF

PCLK

PCLK active edge positive

VSYNC

Pixel Output Pattern

Table 1 shows the output data order from the

OV9625/OV9121. The data output sequence following the

first HREF and after VSYNC is: B0,0 G0,1 B0,2 G0,3â¦

B0,1278 G0,1279. After the second HREF, the output is G1,0

R1,1 G1,2 R1,3â¦ G1,1278 R1,1279â¦, etc. If the

OV9625/OV9121 is programmed to output VGA

resolution data, horizontal and vertical sub-sampling will

occur. The default output sequence for the first line of

output will be: B0,0 G0,1 B0,4 G0,5â¦ B0,1276 G0,1277. The

second line of output will be: G1,0 R1,1 G1,4 R1,5â¦ G1,1276

R1,1277.

Table 1

Data Pattern

R/C

3 . . . 1278

1279

B0,0

G0,1

B0,2

G0,3 . . . B0,1278

G0,1279

G1,0

R1,1

G1,2

R1,3 . . . G1,1278

R1,1279

B2,0

B2,2

G2,3 . . . B2,1278

G2,1279

G3,0

R3,1

G3,2

R3,3 . . . G3,1278

R3,1279

1022 B1022,0 G1022,1 B1022,2 G1022,3

1023 G1023,0 R1023,1 G1023,2 R1023,3

B1022,1278 G1022,1279

G1023,1278 R1023,1279

Proprietary to OmniVision Technologies

Version 1.3, September 15, 2003

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