OV9625 Datasheet, PDF (24/30 Pages) List of Unclassifed Manufacturers – OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP

OV9625/OV9121 CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni ision
Table 11
Address
(Hex)
23
24
25
26
27
28
29
2A
Device Control Register List
Register
Name
ROFF
AEW
AEB
VV
BBIAS
GbBIAS
GrBIAS
COML
Default
(Hex)
EF
A0
88
F4
80
80
80
00
R/W
Description
R Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see “COMG” on page 19)
Bit[7]: Offset direction
RW
0: Add ROFF[6:0]
1: Subtract ROFF[6:0]
Bit[6:0]: R channel offset adjustment value
Luminance Signal High Range for AEC/AGC Operation
RW
AEC/AGC values will decrease in auto mode when average
luminance is greater than AEW[7:0]
Luminance Signal Low Range for AEC/AGC Operation
RW
AEC/AGC values will increase in auto mode when average
luminance is less than AEB[7:0].
Fast Mode Large Step Range Thresholds - effective only in AEC/AGC
fast mode (COMI[7] = 1, see “COMI” on page 21)
Bit[7:4]: High threshold
RW
Bit[3:0]: Low threshold
AEC/AGC may change in larger steps when luminance average is
greater than VV[7:4] or less than VV[3:0].
B Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]: Offset direction
RW
0: Add BBIAS[6:0]
1: Subtract BBIAS[6:0]
Bit[6:0]: B channel offset adjustment value
Gb Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]: Offset direction
RW
0: Add GbBIAS[6:0]
1: Subtract GbBIAS[6:0]
Bit[6:0]: Gb channel offset adjustment value
Gr Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]: Offset direction
RW
0: Add GrBIAS[6:0]
1: Subtract GrBIAS[6:0]
Bit[6:0]: Gr channel offset adjustment value
Common Control L
Bit[7]: Line interval adjustment. Interval adjustment value is in
COML[6:5] and FRARL[7:0] (see “FRARL” on page 25).
0: Disabled
RW
1: Enabled
Bit[6:5]: Line interval adjust value MSB 2 bits
Bit[4]: Reserved
Bit[3:2]: HSYNC timing end point adjustment MSB 2 bits
Bit[1:0]: HSYNC timing start point adjustment MSB 2 bits
24
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003