OV9625 Datasheet, PDF (25/30 Pages) List of Unclassifed Manufacturers – OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP

Omni ision
Register Set
Table 11
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Line Interval Adjustment Value LSB 8 bits
2B
FRARL
00
2C
RBIAS
80
2D
ADDVSL
00
2E
ADDVSH
00
2F
YAVG
00
RW _{The frame rate will be adjusted by changing the line interval. Each LSB}
will add 2/1520 T_frame in SXGA and 2/800 T_frame in VGA mode to the
frame period.
R Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]: Offset direction
RW
0: Add RBIAS[6:0]
1: Subtract RBIAS[6:0]
Bit[6:0]: R channel offset adjustment value
VSYNC Pulse Width LSB 8 bits
RW
Bit[7:0]: Line periods added to VSYNC width. Default VSYNC
output width is 4 x t_line. Each LSB count will add 1 x t_line
to the VSYNC active period.
VSYNC Pulse width MSB 8 bits
RW
Bit[7:0]: Line periods added to VSYNC width. Default VSYNC
output width is 4 x t_line. Each MSB count will add
256 x t_line to the VSYNC active period.
Luminance Average
This register will auto update when COMH[5] = 1 (see “COMH” on
page 20). Average Luminance is calculated from the B/Gb/Gr/R
RW _{channel average as follows:}
(BAVG[7:0] + GbAVG[7:0] + GrAVG[7:0] +RAVG[7:0])/4
HSYNC Position and Width Start Point Lower 8 bits
30
HSDY
08
RW _{This register and COML[1:0] (see “COML” on page 24) define the}
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.
HSYNC Position and Width End Point Lower 8 bits
31
HEDY
30
RW _{This register and COML[3:2] (see “COML” on page 24) define the}
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
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