OV9625 Datasheet, PDF (17/30 Pages) List of Unclassifed Manufacturers – OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP

Omni ision
Register Set
Register Set
Table 11 provides a list and description of the Device Control registers contained in the OV9625/OV9121. The device slave
addresses are 60 for write and 61 for read.
Table 11
Address
(Hex)
00
Device Control Register List
Register
Name
GAIN
Default
(Hex)
00
R/W
Description
AGC – Gain Control
Bit[7:6]: Reserved
RW
Bit[5:0]: Gain control gain setting
• Range: 1x to 8x
Set COMI[0] = 0 (see “COMI” on page 21) to disable AGC
01
BLUE
Blue gain control MSB, 8 bits (LSB 2 bits in COMA[3:2], see “COMA” on
80
RW ^{page 17)}
Note: This function is not available on the B&W OV9121.
02
RED
Red gain control MSB, 8 bits (LSB 2 bits in COMA[1:0], see “COMA” on
page 17)
80
RW
Note: This function is not available on the B&W OV9121.
Common Control A
Bit[7:4]: AWB update threshold
03
COMA
40
RW
Bit[3:2]: BLUE channel lower 2 bits gain control
Bit[1:0]: RED channel lower 2 bits gain control
Note: This function is not available on the B&W OV9121.
Common Control B
Bit[7,4]: AWB – Update speed select
00: Slow
01: Slowest
10: Fast
04
COMB
00
RW
11: Fast
Bit[6:5]: AWB – Step select
00: 1023 steps
01: 255 steps
10: 511 steps
11: 255 steps
Bit[3]: Reserved
Bit[2:0]: AEC lower 3 bits, AEC[2:0] (see “AEC” on page 19 for
most significant 8 bits, AEC[10:3])
05
BAVG
00
RW B Channel Average
06
GbAVG
00
RW G Channel Average - picked G pixels in the same line with B pixels.
07
GrAVG
00
RW G Channel Average - picked G pixels in the same line with R pixels.
08
RAVG
00
RW R Channel Average
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
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