VS1033 Datasheet, PDF (64/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
10. VS1033 REGISTERS
10.13 I2S DAC Interface
The I2S Interface makes it possible to attach an external DAC to the system.
10.13.1 Registers
I2S registers, prefix I2S
Reg Type Reset Abbrev
Description
0xC040 r/w
0 CONFIG[3:0] I2S configuration
10.13.2 Configuration I2S CONFIG
Name
I2S CF MCLK ENA
I2S CF ENA
I2S CF SRATE
I2S CONFIG Bits
Bits Description
3 Enables the MCLK output (12.288 MHz)
2 Enables I2S, otherwise pins are GPIO
1:0 I2S rate, ”10” = 192, ”01” = 96, ”00” = 48 kHz
I2S CF ENA enables the I2S interface. After reset the interface is disabled and the pins are used for
GPIO.
I2S CF MCLK ENA enables the MCLK output. The frequency is either directly the input clock (nom-
inal 12.288 MHz), or half the input clock when mode register bit SM CLK RANGE is set to 1 (24-
26 MHz input clock).
I2S CF SRATE controls the output samplerate. When set to 48 kHz, SCLK is MCLK divided by 8,
when 96 kHz SCLK is MCLK divided by 4, and when 192 kHz SCLK is MCLK divided by 2.
MCLK
SCLK
LROUT
SDATA
MSB
Left Channel Word
LSB MSB
Right Channel Word
Figure 16: I2S Interface, 192 kHz.
To enable I2S first write 0xc017 to SCI WRAMADDR and 0x33 to SCI WRAM, then write 0xc040 to
SCI WRAMADDR and 0x0c to SCI WRAM.
Version 0.6, 2005-01-05
64