VS1033 Datasheet, PDF (20/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
7. SPI BUSES
7.5.2 SCI Read
XCS
SCK
SI
SO
DREQ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
30 31
3210
000000110000
don’t care
don’t care
instruction (read)
0000000000
address
data out
15 14
000000
10
X
execution
Figure 6: SCI Word Read
VS1033 registers are read from using the following sequence, as shown in Figure 6. First, XCS line is
pulled low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed by
an 8-bit word address. After the address has been read in, any further data on SI is ignored by the chip.
The 16-bit data corresponding to the received address will be shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
DREQ is driven low for a short while when in a read operation by the chip. This is a very short time and
doesn’t require special user attention.
7.5.3 SCI Write
XCS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
30 31
3 2 1 0 15 14
000000100000
10
X
instruction (write)
address
data out
0000000000000000 00
0 0X
DREQ
execution
Figure 7: SCI Word Write
VS1033 registers are written from using the following sequence, as shown in Figure 7. First, XCS line
is pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed
by an 8-bit word address.
Version 0.6, 2005-01-05
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