VS1033 Datasheet, PDF (19/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
7. SPI BUSES
7.4.3 SDI in VS1001 Compatibility Mode
BSYNC
SDATA
DCLK
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4: BSYNC Signal - one byte transfer.
When VS1033 is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure
correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending
on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first
order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiver
stays active and next 8 bits are also received.
BSYNC
SDATA
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DCLK
Figure 5: BSYNC Signal - two byte transfer.
7.4.4 Passive SDI Mode
If SM NEWMODE is 0 and SM SDISHARE is 1, the operation is otherwise like the VS1001 compat-
ibility mode, but bits are only received while the BSYNC signal is ’1’. Rising edge of BSYNC is still
used for synchronization.
7.5 Serial Protocol for Serial Command Interface (SCI)
7.5.1 General
The serial bus protocol for the Serial Command Interface SCI (Chapter 8.5) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes
are always send MSb first. XCS should be low for the full duration of the operation, but you can have
pauses between bits if needed.
The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.
See table below.
Instruction
Name Opcode
Operation
READ 0b0000 0011 Read data
WRITE 0b0000 0010 Write data
Note: VS1033 sets DREQ low after each SCI operation. The duration depends on the operation. It is not
allowed to start a new SCI/SDI operation before DREQ is high again.
Version 0.6, 2005-01-05
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