VS1033 Datasheet, PDF (21/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
7. SPI BUSES
After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the
WRITE sequence.
After the last bit has been sent, DREQ is driven low for the duration of the register update, marked “exe-
cution” in the figure. The time varies depending on the register and its contents (see table in Chapter 8.6
for details). If the maximum time is longer than what it takes from the microcontroller to feed the next
SCI command or SDI byte, it is not allowed to finish a new SCI/SDI operation before DREQ has risen
up again.
7.6 SPI Timing Diagram
XCS
SCK
tXCSS
0
1
tWL tWH
14
15
16
tXCSH
30
31
tXCS
SI
SO
tZ
tH
tSU
tV
tDIS
Figure 8: SPI Timing Diagram.
Symbol Min
Max Unit
tXCSS
5
ns
tSU
-26
ns
tH
2
CLKI cycles
tZ
0
ns
tWL
2
CLKI cycles
tWH
2
CLKI cycles
tV
2 (+ 25ns¹) CLKI cycles
tXCSH -26
ns
tXCS
2
CLKI cycles
tDIS
10 ns
1 _{25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.}
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can easily be used is 1/6 of VS1033’s internal clock speed CLKI. Slightly higher speed can be
achieved with very careful timing tuning. For details, see Application Notes for VS10XX.
Note: Although the timing is derived from the internal clock CLKI, the system always starts up in 1.0×
mode, thus CLKI=XTALI.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
Version 0.6, 2005-01-05
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