VS1033 Datasheet, PDF (33/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
8. FUNCTIONAL DESCRIPTION
SM STREAM activates VS1033’s stream mode. In this mode, data should be sent with as even intervals
as possible and preferable in blocks of less than 512 bytes, and VS1033 makes every attempt to keep its
input buffer half full by changing its playback speed upto 5%. For best quality sound, the average speed
error should be within 0.5%, the bitrate should not exceed 160 kbit/s and VBR should not be used. For
details, see Application Notes for VS10XX. This mode only works with MP3 and WAV files.
SM DACT defines the active edge of data clock for SDI. When ’0’, data is read at the rising edge, when
’1’, data is read at the falling edge.
When SM SDIORD is clear, bytes on SDI are sent MSb first. By setting SM SDIORD, the user may
reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however, still sent in the
default order. This register bit has no effect on the SCI bus.
Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 7.2, if
also SM SDINEW is set.
Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 7.2.1 and 7.4.2.
Note, that this bit is set as a default when VS1033 is started up.
By activating SM ADPCM and SM RESET at the same time, the user will activate IMA ADPCM record-
ing mode. More information is available in the Application Notes for VS10XX.
If SM ADPCM HP is set at the same time as SM ADPCM and SM RESET, ADPCM mode will start
with a high-pass filter. This may help intelligibility of speech when there is lots of background noise.
The difference created to the ADPCM encoder frequency response is as shown in Figure 13.
VS1023 AD Converter with and Without HP Filter
5
No High−Pass
High−Pass
0
−5
−10
−15
−20
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency / Hz
Figure 13: ADPCM Frequency Responses with 8 kHz sample rate.
SM LINE IN is used to select the input for ADPCM recording. If ’0’, microphone input pins MICP and
MICN are used; if ’1’, LINEIN is used.
SM CLK RANGE activates a clock divider in the XTAL input. When SM CLK RANGE is set, from
the chip’s point of view e.g. 24 MHz becomes 12 MHz. SM CLK RANGE should be set as soon as
possible after a chip reset.
Version 0.6, 2005-01-05
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