MFC2000 Datasheet, PDF (60/426 Pages) List of Unclassifed Manufacturers – Multifunctional Peripheral Controller 2000

MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
4.3.2 Register Description
SIU Control
Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default
SIU Configuration (Not Used)
(SIUConfig)
01FF8801
(Not Used) (Not Used) (Not Used) (Not Used)
(Not Used)
(Not Used)
CS4n Read
Only
Rst. Value
xxxxxxx0b
Read Value
00h
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
SIU Configuration CS3n Write
(SIUConfig)
Only
01FF8800
Flush
Cache
Global Lock Cache Lock Cache Test Cache
Mode
Mode
Enable
Disable
Force
External
Disable
Abort
Rst. Value
00h
Read Value
00h
Bit 8
CS4n Read only
Writing a 1 makes CS4n a read only CS. Default is 0.
Bit 7
CS3n Write only
Writing a 1 makes CS3n a write only CS. Default is 0.
Bit 6
Flush: Write only bit.
Writing a 1 generates a pulse which flushes all Valid bits, LRU bits and
Lock bits in the Cache Tag. Default is 0
Bit 5
Global_Lock: Read/writable bit Writing a 1 locks the whole Cache. The Cache stays in Lock Mode
until a 0 is written. Default is 0.
Bit 4
Cache_Lock: Read/writable bit Writing a 1 places the Cache in the Lock Mode and the Cache stays in
Lock Mode until a 0 is written. Each cache line is locked individually .
Default is 0
Bit 3
Cache_Test: Read/writable bit
Writing a 1 sets the Cache into Test Mode and the Cache RAM and
Tags can be accesses as regular memory. Note that certain Tag bit
only readable . The Cache stays in Test Mode until a 0 is written to
this bit. Default is 0.
Bit 2
Cache_Enable: Read/writable bit
Writing a 1 enables the Cache and the Cache stays enabled until a 0
is written or a reset is received. Power-up resets to 0, so the Cache is
disabled.
Bit 1
Force_external
This signal will disable the forcing of all accesses to be visible on the
external bus regardless of destination. If this signal is enabled, only
external transactions will be visible on the external bus. 1 is disabled,
0 is enabled. Default is 0.
Bit 0
Disable_abort:
This signal disables abort generation for internal and external access.
If this signal is a 1, all transactions to internal and external address
space will be allowed to occur regardless of if an valid internal or
external peripheral exists. If this signal is 0, then accesses must be to
valid peripheral locations or an abort signal will be generated. Default
is 0.
4-30
Conexant
100723A