MFC2000 Datasheet, PDF (274/426 Pages) List of Unclassifed Manufacturers – Multifunctional Peripheral Controller 2000

MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
Address
Bit 15
T4 FIFO Bits
Remaining Register
(T4FIFOBitRem)
$01FF817B
(Not Used)
Address
Bit 7
T4 FIFO Bits
Remaining Register
(T4FIFOBitRem)
$01FF817A
(Not Used)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
(Not Used) (Not Used) (Not Used) (Not Used) (Not Used)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
(Not Used) (Not Used) (Not Used) Bits remaining
Bit 9
(Not Used)
Bit 1
Bit 8
Default
(Not Used)
Rst. Value
xxh
Read Value:
00h
Bit 0
Default
Rst. Value
xxxx0000b
Read Value
x0000000b
Bit 15-4:
Bit 3-0:
Not used
Number of bits remaining in FIFO (holding register), with values
ranging from 0 to 15. The interpretation of bits remaining depends on
the direction of data flow. If the compressor/decompressor is emptying
the FIFO, bit remaining is the number of that contain data that have
yet to be processed. If the compressor/decompressor is filling the
FIFO, bits remaining is the number of bits that are empty.
T.4 data FIFO halfword[3:0] for the coded data to/from the external memory (for DMA channel 10):
Address:
T.4 Data FIFO
(T4Data1FIFOx)
Bit 15
data
bit 15
Bit 14
data
bit 14
Bit 13
data
bit 13
Bit 12
data
bit 12
Address:
T.4 Data FIFO
(T4Data1FIFOx)
Bit 7
data
bit 7
Bit 6
data
bit 6
Bit 5
data
bit 5
Bit 4
data
bit 4
Bit 11
data
bit 11
Bit 3
data
bit 3
Bit 10
data
bit 10
Bit 9
data
bit 9
Bit 2
data
bit 2
Bit 1
data
bit 1
Bit 8
data
bit 8
Bit 0
data
bit 0
Default:
Rst Value
xxh
Read
Value xxh
Default:
Rst Value
xxh
Read
Value xxh
• Address assignment for T.4 Data FIFO halfword[3:0]
FIFO halfword
FIFO halfword 3
FIFO halfword 2
FIFO halfword 1
FIFO halfword 0
The register name
T4DataFIFO3
T4DataFIFO2
T4DataFIFO1
T4DataFIFO0
Address
01FF8117-16
01FF8115-14
01FF8113-12
01FF8111-10
14-8
Conexant
100723A