MFC2000 Datasheet, PDF (119/426 Pages) List of Unclassifed Manufacturers – Multifunctional Peripheral Controller 2000

Hardware Description
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bit 4-0:
MFC 2000 Multifunctional Peripheral Controller 2000
If the Bit Rotation Block is selected (bit 6 = 0), and the external data
bus for the Print ASIC is byte wide, this bit needs to be ‘0’. If the Bit
Rotation Block is selected (bit 6 = 0), and the external data bus for the
Print ASIC is halfword wide, this bit needs to be ‘1’. If external memory
is selected (bit 6 = 1), the external bus data width for the Print ASIC
and external memory need to be matched (this bit is not used).
Control bit definition is with reference to the DMA requested device
and controls the read/write signals during the DMA cycle. If it is set to
write, the write strobe will be active during the DMA cycle.
If the Bit Rotation Block is selected ( bit 6 = 0), the DMA Request will
be held off when the Bit Rotation Block output register is not ready.
The ASIC output bus drivers will be disabled during external DMA
request write (bit 6 = 1 and bit 7 = 0).
Controls the address count direction performed after each DMA cycle.
These bits control how the address registers will count after each DMA
cycle. Note: If byte mode is set, the Count By 1 should be set.
Note: Requests to this channel are delayed by two clocks for synchronization.
Address:ch2csbs Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
DMA 2 Transfer
Block Size Reg.
(DMA2BlockSize)
Channel 2 Not Used
Enable = 1
Not Used
Not Used
Not Used
$xx81B5
Address:ch2csbs Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DMA2 Transfer
Block Size Low
Byte Reg.
Low Byte Value for the External DMA Block Size Counter
(DMA2BlockSizeLo)
$xx81B4
Bit 10
Not Used
Bit 2
Bit 9
Bit 8
Default:
Upper two bits of the Block Rst. Value
Size counter
00h
Read
Value 00h
Bit 1
Bit 0
Default:
Rst. Value
00h
Read
Value 00h
• DMA Channel 2 Block Size Limit Counter
• block size of DMA channel 2 (halfwords)
− Unlimited block size (block size = ∞ ):
bit[7:0] of the DMA2BlockSize register = 00h
bit[9:8] of the DMA2BlockSize register = 00b.
− Limited block size (block size = 1 - 1023)
• The Block Size counter will decrement regardless of the DMA Address counter’s activity. The block size
register content is 0000h when the block size limit is reached.
• Please see the operation description of DMA2BlkSize and DMA2BufBlkSize registers below (in the
DMA2BufBlkSize register section).
• Writing to this register will also clear the DMA channel 2 interrupt.
Bit 15:
Channel 2 Enable is cleared when the block size limit is reached, and
must be set, (enabled) after a new block size is entered. The block
size can only be written into the DMA2Blksize register when this bit is
0.
100723A
Conexant
4-89