MFC2000 Datasheet, PDF (304/426 Pages) List of Unclassifed Manufacturers – Multifunctional Peripheral Controller 2000

MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
Address:
USBEP2Ctrl
(R/W)
$01FF85AB
Address:
USBEP2Ctrl
(R/W)
$01FF85AA
Bit 15 Bit 14 Bit 13
Fifo Enabled Data
Fifo Ready
(Read Only) ^Request
(Read Only)
Bit 12 Bit 11
Fifo DMA Threshold
Bit 7
unused
Bit 6
Bit 5
Bit 4
Bit 3
Holding Reg Byte Present Fifo Data Quantity
Full
Bit 10
Bit 2
Bit 9
Bit 8
Fifo Output Pointer
Bit 1
Bit 0
Fifo Input Pointer
Default:
Rst. Value
00h
Read Value
00h
Default:
Rst. Value
x0000000b
Read Value
00h
Bit 15:
Bit 14:
Bit 13:
Bit 12-10:
Bit 9-8:
Bit 7:
Bit 6:
Bit 5:
Bit 4-2:
Bit 1-0:
This bit indicates that the FIFO is active and capable of generating
DMA requests. This bit generally follows the setting of the LCL_ENB
input signal except the FIFO Enabled register bit will remain asserted
if the LCL_ENB input signal is set to false while the FIFO is executing
a DMA transfer. In this case, the register bit will remain set for the
duration of the DMA transfer and then become cleared.
This bit is similar to the DMA_REQ signal except that it is not blocked
when DMA_TC0 is set. It indicates that the programmed threshold has
been met or exceeded and that the FIFO requires data transfers either
by enabling hardware DMA through DMA_TC0 or by executing
software DMA cycles.
This bit indicates that the FIFO can accept data transfers to/from the
local logic. This bit is low when the data direction is into the local logic
and the FIFO is empty or when the data direction is out of the local
logic and the FIFO is full.
This bit field indicates at which point the FIFO should issue a DMA
request. It is compared with the FIFO Data Quantity bit field to
determine when this should occur. Legal values are from
1 to 4. A value of zero causes no data transfers to occur. Values
greater than 4 are treated as 4.
This bit field indicates which byte of the FIFO quad halfword structure
is the next to be used as output data.
Not used
This bit indicates that there is a full word in the holding register.
This bit indicates that there is a single byte in the holding register.
This bit field indicates the number of quad halfwords that contain data.
Valid values are from 0 to 4.
This bit field indicates which byte of the FIFO quad halfword structure
is the next to receive input data.
16-6
Conexant
100723A