MFC2000 Datasheet, PDF (35/426 Pages) List of Unclassifed Manufacturers – Multifunctional Peripheral Controller 2000

Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
Flash Memory Chip Selects (FCS1n and FCS2n)
FCS0n and FCS1n are multiplexed with PWM[1] and PWM[2] and output through FCS0n/PWM[1] and
FCS1n/PWM[2] pins. After reset, the Flash disable bit (bit 0) of the FlashCtrl register is 0 and the FCS0n/PWM[1]
and FCS1n/PWM[2] pins are used as FCS0n and FCS1n. FCS0n and FCS1n can access either NOR-type
(default) or NAND-type flash memory, selectable with the NANDFlashEnb bit (bit 6) of the FlashCtrl register.
When enabled for NOR-type flash memory (default), FCS1n can be activated by accessing the 2-MB
(00A00000h-00BFFFFFh) flash memory address area. FCS0n can be activated by accessing the 2-MB
(00800000h - 009FFFFFh) flash memory address area. Firmware controls the flash memory access block size. If
enabled for NAND-type flash memory, FCS0n and FCS1n revert to the GPO function and output bit 9 and bit 8
values of the FlashCtrl register . 0 to 7 (default) wait states and normal (default) or early off of the write strobe can
be chosen using the FlashCtrl register described in the SIU section.
Modem Chip Select (MCSn)
The 128 kB address space from 00C20000h to 00C2FFFFh is reserved for the external modem and selected with
MCSn. It is muxed with the M_STROBE signal of the modem IA on the pin. M_STROBE is usually used to
interface the embedded DSP to the external modem IA if the embedded V.34 modem DSP is used. MCSn can be
selected and muxed out for the external modem if the embedded modem DSP is not used. MCSn can be
programmed for 0 to 7 (default) wait states, 0 (default) or 1 read and write strobe on delays, and normal (default)
or early write strobe off times using the MCSCtrl register.
P80 Chip Select (P80_CSn)
Address space form 00C3000 to 00C7FFF has been reserved for the P80 functions.
Smart Data Access Arraignment (SDAA_CSn)
Address space form 00C3800 to 00CFFFF has been reserved for the SDAA functions.
4.1.1.4 External I/O Chip Selects
Chip Select [2] (CS2n)
The 512 kB address space from 00C80000h to 00CFFFFFh is selected using the external I/O chip selects CS2n.
GPIO[4] (default) can be configured as CS2n using the GPIO[4]/CS2n bit of the GPIOConfig register. CS2n can
be programmed for 0 (default) to 7 wait states, 0 (default) to 3 read and write strobe delays, and normal (default)
or early write strobe off times using the CS2Ctrl register.
Chip Select [4:3] (CS4n-CS3n)(optional)
The 256 kB address space from 00C40000h to 00C7FFFFh can optionally be selected using the two external I/O
chip selects CS4n and CS3n. These chip selects are configured identically to CS2n.
GPIO[6] (default) can be configured as CS4n using the GPIO[6]/CS4n bit of the GPIOConfig register. Likewise,
GPIO[5] (default) can be configured as CS3n by using the GPIO[5]/CS3n bit in the GPIOconfig1 register.
The top 128 kB (00C40000h to 00C5FFFFh) are addressed by CS4n. CS4n is active for read-access only
(internally gated with the read strobe) when the CS4nReadOnly bit (bit 8) of the SIUConfig register is 1. CS4n is
active for both read and write access when the CS4nReadOnly bit (bit 8) of the SIUConfig register is 0. The next
128 kB (00C60000h to 00C7FFFFh) is addressed by CS3n. CS3n is active for write-access only (internally gated
with the write even strobe) when the CS3nWriteOnly bit (bit 7) of the SIUConfig register is 1. If the external I/O
device using CS3n is a 16-bit device, 16-bit access must be done. No high-byte or low-byte access can be done.
CS3n is active for both read and write access when the CS3nWriteOnly bit (bit 7) of the SIUConfig register is 0.
Chip Select 1 (CS1n)
The next address range below those of CS4n-CS2n is the 1-MB range (00D00000h to 00DFFFFFh) selected by
CS1n. CS1n can be programmed for 0 (default) to 7 wait states, 0 (default) to 3 read and write strobe delays, and
normal (default) or early write strobe off times using the CS1Ctrl register.
100723A
Conexant
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