MFC2000 Datasheet, PDF (321/426 Pages) List of Unclassifed Manufacturers – Multifunctional Peripheral Controller 2000

Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
16.3 Firmware Operation
16.3.1 Setup Transfer
During the setup transfer, a setup interrupt will be generated to the ARM. ARM can determine it is a setup
interrupte by reading the interrupt register and clear the interrupt by setting the clear endpoint 0 or 5 setup
interrupt bit of the USBClrIrq register. The 8 bytes of setup packet data can be read from the endpoint 0 or 5
setup buffer.
16.3.1.1 USB Standard Commands
Since the UDC core decodes and acts upon the USB standard commands except Get_Descriptor, the setup
packet data of all standard commands (except Get_Descriptor ) will not be stored in the setup buffers neither the
setup interrupt will be generated during a starndard command transfer.
16.3.1.2 Get_Descriptor Command
The Get_Descriptor command is supported by endpoint 0. The ARM needs to decode the setup packet and load
the descriptor data into the endpoint 0 buffer then set the ep0 read buffer written bit.
16.3.2 Control Read Transfer
During a control read transfer, an interrupt will be generated along with read status bit after the data in the
ep0/ep5 buffer are send to the host. ARM can determine the type of interrupt by reading the interrupt register and
clear the interrupt by setting the corresboing bit in the clear interrupt register. ARM needs to check the ep0/ep5
read status bit to find out if the control read is successful or not.
16.3.3 Control Write Transfer
During a control write transfer, the data from the PC will be written to an internal buffer first. After the control write
transfer finished, an interrupt along with write status bit will be generated. ARM can determine the interrupt by
reading the interrupt register and clear the interrupt by writing to the corresbonding bit in the clear_interrupt
register. Then ARM can read data from the endpoint 0 or endpoint 5 data buffers. After all the data have been
read , ARM will set the endpoint 0 or endpoint 5 write_buffer_read bit in the endpoint status register.
16.3.4 BULK_IN Transfer
The MaxPacketSize for both bulk in pipes are 64 bytes. DMA channel 0 is assigned to USB and it has four logic
channels. Endpoint 1 and 3, which are bulk in endpoints, are assigned to logic channel 0 and 2. The procedures
of programming the registers are:
1. Enable DMA channel 0 by writing 1 to bit[0] of DMA 0 configuration register.
2. Enable logic channel 0 or 2 and set logic channel 0 or 2 to be read mode by setting the corresbonding bits in
DMA 0 configuration register.
3. Set memory address in DMAUSB0CntLo and DMAUSB0CntHi or DMAUSB2CntLo and DMAUSB2CntHi.
4. Define block size in DMAUSB0BlkSiz or DMAUSB2BlkSiz.
5. If more than one memory block is needed, repeat step 3 and 4 to set desired memory blocks.
6. Load 4 half words into endpoint 1 or 3 internal fifo by writing to endpoint 1 or 3 data port register and transition
register OR by writing to the endpoint 1 or 3 halfword fifos.
7. Set endpoint 1 or 3 control register.
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Conexant
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