PT7A4410 Datasheet, PDF (6/34 Pages) List of Unclassifed Manufacturers – T1/E1/OC3 System Synchronizer

Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Table 2. Pin Description (continued)
Pin
Name
Type
Descr iption
25
C8
O 8.192 MHz clock (CMOS): This output is used for ST-BUS operation at 8.192Mb/s.
26
C16
O
16.384 MHz clock (CMOS): This output is used for ST-BUS operation with a
16.384MHz clock.
27
C6
O Clock 6.312 MHz (CMOS Output). This output is used for DS2 applications.
29
HOLDOVER
O
Holdover (CMOS Output). This output goes to a logic high whenever the digital PLL
goes into holdover mode.
Guar d Time (Schmitt input):The signal at this pin is used by the device’s state machine
in both Manual and Automatic modes to effect the TIE function and the state changes
30
GTi
I between Primary Holdover and Primary Normal, and Primary Holdover and Secondary
Normal. Refer to Tables 6 and 7. The signal at this pin is clocked in by the rising edge
of F8.
Guar d Time (CMOS): The LOS1 input is clocked in by the rising edge of F8, then
32
GTo
O buffered and sent to GTo when in Automatic Mode. This pin is typically used to drive
GTi input through an RC circuit.
Secondar y Reference Loss (TTL): This pin is normally connected to an external source
33
LOS2
I
that applies high logic level whenever the secondary reference signal is lost or invalid.
The existing level at this pin is clocked in by the rising edge of F8. This pin is internally
pulled down to GND.
Pr imar y Reference Loss (TTL): A high level is applied on this pin when the Primary
34
LOS1
I reference signal is lost or invalid. Refer to pin description of LOS2. This pin is internally
pulled down to GND.
35
TDO
O
Test Ser ial Data Out (TTL Output). JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Mode/Contr ol Select 2 (TTL): Along with MS1, determines the operating modes
36
MS2
I (Manual or Automatic) and operating states when in Maunal mode (Normal, Holdover or
Free-Run).
37
MS1
I
Mode/Control Select 1 (TTL): Refer to pin description of MS2. This pin is internally
pulled down to GND.
Reference Source Select (TTL): In Manual mode, low logic level at this pin selects the
38
RSEL
I
Primary Reference as the input reference signal and a high level selects the Secondary.
For Automatic mode, this pin must always be maintained at low logic level. This pin is
internally pulled down to GND.
39
TEST
I
Test (TTL Input). This input is normally tied low. When pulled high, it enables internal
test modes. This pin is internally pulled down to GND.
Frequency Select 2 (TTL):Together with FS1, selects one of the three DPLL feedback
40
FS2
I frequencies to match the desired Input Reference Frequency (8 kHz, 1.544 MHz or 2.048
MHz).
41
FS1
I Frequency Select 1 (TTL): Refer to the pin description of FS2.
42
TDI
I ^{Test Ser ial Data In (TTL Input). JTAG serial test instructions and data are shifted in on}
this pin. This pin is internally pulled up to V_CC..
Reset (Schmitt): RST Resets the device when at low logic level. Reset is needed whenever
43
RST
I
the operating mode is changed, or the reference signal frequency is switched or when
power-up; so as to ensure proper operation of the device. Following Reset, the output
clocks and frame signals are phase-aligned with the input reference source.
44
TMS
I
Test Mode Select (TTL Input). JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to V_CC..
PT0106(09/02)
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